Among various display schemes for liquid crystal displays, EL displays, and like matrix displays, one that achieves a high definition display is an active matrix scheme using TFTs (Thin Film Transistors) as switching elements.
A TFT-based liquid crystal display will be described as a typical example of the active matrix display in reference to FIG. 13 showing a block diagram of its construction. The display and its display scheme constitute related art to this invention.
The liquid crystal display is formed of a liquid crystal display section and a liquid crystal drive device which drives the display section. The liquid crystal display section includes a TFT liquid crystal panel 901.
The liquid crystal panel 901 is provided in it with liquid crystal display elements (not shown) and an opposite electrode (common electrode) 907. Meanwhile, the liquid crystal drive device includes: a source drive circuit 902A composed of source drivers 902 each built around an IC (Integrated Circuit); a gate drive circuit 903A composed of gate drivers 903 each built around an IC; a controller 904; a liquid crystal drive power source 905; and an opposite electrode drive circuit 906 which controls the electric potential of the opposite electrode 907.
The source driver 902 and the gate driver 903 are typically constructed (packaged) either by connecting a wired insulating film with an IC chip mounted thereon, for example, a TCP (Tape Carrier Package), to ITO (Indium Tin Oxide) or other terminals of the liquid crystal panel 901 or by thermally compressing a bare IC chip to ITO or other terminals of the liquid crystal panel 901 with an intervening ACF (anisotropic conductive film). FIG. 13 illustrates the construction by way of functions of individual components.
The controller 904 supplies digitized display data (for example, RGB signals representing red, green, and blue colors) D and various control signals to the source drivers 902 and various control signals to the gate drivers 903. Primary control signals fed to the source drivers 902, collectively designated S1 in the figure, include a horizontal synchronization signal (latch signal), a source driver start pulse signal, and a source driver clock signal. Primary control signals fed to the gate drivers 903, collectively designated S2 in the figure, include a vertical synchronization signal and a gate driver clock signal. A power source which drives the IC chips is omitted in the figure.
The liquid crystal drive power source 905 supplies voltage (e.g., reference voltage VR which will be detailed later) for liquid crystal panel display to the source drivers 902 and the gate drivers 903.
The display data, externally fed, is supplied to the source drivers 902 through the controller 904 as the display data D in the form of a digital signal.
The source drivers 902 latch the display data D from the controller 904 by time division and convert the display data D from digital to analog in synchronism with the horizontal synchronization signal (alternatively, “latch signal LS” (see FIG. 14)) from the controller 904. The source drivers 902 then supply a tone display analog voltage (tone display voltage, data signal) obtained by the DA conversion from liquid crystal drive voltage output terminals to the liquid crystal display elements (not shown), in the liquid crystal panel 901, associated with the liquid crystal drive voltage output terminals via source signal lines (data signal lines; not shown). The gate drivers 903 supply a scan signal to gate signal lines (scan signal lines; not shown) to select a gate signal line.
FIG. 14 shows a block diagram of the construction of the source drivers 902. The following description deals only with basics. Although nothing will be mentioned here about the source driver 902 in the last stage, it is arranged identically to those in the other stages which will be described, except that the former does not output a cascade output signal S.
Each source driver 902 includes an input latch circuit 1011, a shift register circuit 1012, a sampling memory circuit 1013, a hold memory circuit 1014, a level shifter circuit 1015, a DA converter circuit 1016, an output circuit 1017, and a standard voltage generating circuit 1019.
The display data (digital signal) DR, DG, DB (for example, 6 bit each) fed from the controller 904 is temporarily latched in the input latch circuit 1011. The display data DR, DG, DB corresponds to red, green, and blue.
Meanwhile, the start pulse signal SP controlling the transfer of the display data DR, DG, DB is transferred in the shift register circuit 1012 in synchronism with a clock signal CK, and output as an output signal S from the stages (flip-flops) in the shift register circuit 1012 to the sampling memory circuit 1013 and also as a cascade output signal S (start pulse signal SP for the source driver 902 in a next stage) from the last stage in the shift register circuit 1012 to the source driver 902 in a next stage.
The display data DR, DG, DB latched by the previous input latch circuit 1011 in synchronism with the output signals from the stages in the shift register circuit 1012 is temporarily stored in the sampling memory circuit 1013 by time division and output to the next hold memory circuit 1014.
As the sampling memory circuit 1013 holds display data for one horizontal synchronization period, the hold memory circuit 1014 acquires an output signal from the sampling memory circuit 1013 in accordance with the horizontal synchronization signal (latch signal LS), outputs the signal to the next level shifter circuit 1015, and holds the display data until it is fed with a next horizontal synchronization signal.
The level shifter circuit 1015 is to convert the level of the output signal (display data) from the hold memory circuit 1014 by, for example, stepping it up, to a level within a such range that the signal can be appropriately converted in a DA converter circuit 1016 in a next stage to an application voltage (analog voltage) to the liquid crystal panel 901.
The standard voltage generating circuit 1019 generates as many analog voltages for tone display as tones in accordance with a reference voltage VR from the liquid crystal drive power source 905 (see FIG. 13) for output to the DA converter circuit 1016.
The DA converter circuit 1016 selects an analog voltage from the analog voltages (tone display voltages), as many as the tones, supplied by the standard voltage generating circuit 1019 in accordance with the display data level-converted by the level shifter circuit 1015. The analog voltage representing a tone display is fed from the liquid crystal drive voltage output terminals (hereinafter, simply “output terminals”) 1018 to the source signal lines of the liquid crystal panel 901 via the output circuit 1017.
The output circuit 1017 is basically a buffer circuit and built around, for example, a voltage follower circuit using a differential amplifier circuit.
Next, the standard voltage generating circuit 1019 and the DA converter circuit 1016 will be described in terms of circuit construction in more detail which is especially relevant to the present invention.
FIG. 15 shows a circuit diagram of a construction example of the standard voltage generating circuit 1019 as related art. Assuming that digital display data contains, for example, 6 bits for each of RGB (18-bit color), the standard voltage generating circuit 1019 outputs 64 analog voltages V0-V63 which correspond to a display of 26=64 tones. The following will describe a specific construction.
The standard voltage generating circuit 1019, in its simplest form, is built around a resistance dividing circuit in which resistors R0-R7 are connected in series.
Each resistor R0-R7 is 8 resistive elements connected in series. Taking the resistor R0 as an example, it is formed by 8 resistive elements R01, R02, . . . R08 connected in series as shown in FIG. 16.
The remaining resistors R1-R7 are also formed by 8 resistive elements connected in series, identically to the resistor R0. Therefore, the whole standard voltage generating circuit 1019 is formed by 64 resistive elements connected in series.
The standard voltage generating circuit 1019 has 9 halftone voltage input terminals, one for each of 9 reference voltages V′0, V′8, . . . V′56, and V′64. The resistor R0 is connected at an end thereof to a halftone voltage input terminal corresponding to the reference voltage V′64 and at its other end, that is, the connection between the resistor R0 and the resistor R1, to a halftone voltage input terminal corresponding to the reference voltage V′56.
Similarly, halftone voltage input terminals corresponding to the reference voltages V′48, V′40, . . . V′8 are connected respectively to the connections between adjacent ones of the resistors R1, R2, R3, R4, . . . , R6, and R7. The resistor R7 is connected at an end thereof opposite the connection with the resistor R6 to a halftone voltage input terminal corresponding to the reference voltage V′0.
The construction makes available the voltages V1-V63 appearing at the nodes between adjacent ones of the 64 resistive elements and the voltage V0 obtained straightly from the reference voltage V′0, in other words, a total of 64 tone display analog voltages V0-V63. In short, the standard voltage generating circuit 1019, if constructed from resistance dividing circuits, supplies the voltages (tone display analog voltages) V0-V63 to the DA converter circuit 1016.
Incidentally, in typical situations, the halftone voltage input terminals at both ends are always fed with the reference voltages V′0 and V′64 respectively. Meanwhile, the 7 halftone voltage input terminals corresponding to remaining V′8-V′56 are used for fine adjustment and may not actually be fed with voltage.
Next, the DA converter circuit 1016 will be described. FIG. 17 shows a construction example of the DA converter circuit 1016 as related art. In the figure, 1017 represents the aforementioned output circuit and is built around a voltage follower circuit here.
In the DA converter circuit 1016, analog switches are laid out so as to select and output one of the 64 incoming voltages V0-V63 in accordance with display data represented by a 6-bit digital signal. That is, the analog switches are turned on/off in accordance with each bit (Bit0 to Bit5) of display data represented by a 6-bit digital signal. Thus, one of the 64 incoming voltages is selected and output to the output circuit 1017. The analog switch is constructed from, for example, a MOS (metal oxide semiconductor) transistor or transmission gate.
The following will describe the layout of the analog switches.
According to the 6-bit digital signal (display data), Bit0 is the least significant bit (LSB), and Bit5 is the most significant bit (MSB). The analog switches (hereinafter, simply, “switches”) are arranged in pairs. 32 switch pairs (64 switches) are assigned to Bit0, and 16 switch pairs (32 switches) are assigned to Bit1.
Similarly, assigned switching pairs are reduced in half in number for each higher bit, until a single switch pair (2 switches) are assigned to Bit5. Therefore, in total, there are involved 25+24+23+22+21+1=63 switch pairs (126 switches).
An end of each switch assigned to Bit0 form a terminal where a previous voltage V0-V63 is fed. The other end of the switch is paired with such an end of another switch, both ends being connected to an end of a switch assigned to next Bit1. The same arrangement is repeated all the way down to the switch assigned to Bit5, where a line is drawn from the switch assigned to Bit5 and connects to the output circuit 1017.
The switch groups assigned to Bit0 to Bit5 will be referred to as the switch groups SW0-SW5 respectively. The switches in the switch groups SW0-SW5 are controlled through the 6-bit digital signal (display data) Bit0 to Bit5 as in the following. In the switch groups SW0-SW5, one of the paired analog switches (the lower switch in the figure) is in the “on” state when the corresponding bit is a 0 (LOW). Conversely, the other analog switch (the upper switch in the figure) is in the “on” state when the corresponding bit is a 1 (HIGH).
The figure shows Bit0 to Bit5 representing “111111” with the upper switch in each pair in the “on” state and the lower switch in the “off” state. The DA converter circuit 1016 is supplying the voltage V63 to the output circuit 1017.
Similarly, the DA converter circuit 1016 supplies to the output circuit 1017, for example, the voltage V62 when Bit0 to Bit5 are “111110,” the voltage V1 when “000001,” and the voltage V0 when “000000.” One of the tone display analog voltages V0-V63 in accordance with a digital display is thus selected to effect a tone display.
Typically, each source driver IC has one standard voltage generating circuit 1019 which is shared for use among multiple output terminals. In contrast, one DA converter circuit 1016 and one output circuit 1017 are provided to each output terminal 1018.
In a color display, a different output terminal 1018 is used for each color, in which case, each DA converter circuit 1016 and output circuit 1017 are used for a different pixel and for a different color.
In other words, supposing that the liquid crystal panel 901 has N pixels in the longitudinal direction (horizontal line direction) and that the output terminals 1018 are denoted by R, G, B (respectively representing red, green, blue colors the terminals are assigned to) and suffixes n (n=1, 2, . . . , N), the output terminals 1018 are designated R1, G1, B1, R2, G2, B2, . . . , RN, GN, BN. This means that 3N DA converter circuits 1016 and output circuits 1017 are needed.
A liquid crystal device of the aforementioned type is disclosed in Japanese patent application publication Tokukai 2000-183747 (published on Jun. 30, 2000) which is a counterpart to the U.S. Pat. No. 6,373,419.
Incidentally, to effect a natural tone display on an actual liquid crystal display of related art, differences are adjusted between the light transmittance properties of the liquid crystal material and man's visual traits by γ correction. In γ correction, the standard voltage generating circuit 1019 typically generates various tone display analog voltage values by dividing internal resistance unequally rather than equally.
FIG. 18 shows a relationship between tone display data (digital display data) and liquid crystal drive output voltages (tone display analog voltage) of the related art after γ correction. As shown in the figure, zigzag line properties are imparted to the tone display analog voltage with respect to digital display data.
To realize the properties, in the standard voltage generating circuit 1019 in FIG. 15, each resistor R0, . . . , R7 is internally divided into 8 identical parts, and has such a resistance value that will realize the aforementioned γ correction.
In other words, the γ correction is effected by specifying, for example, the 8 resistive elements R01, R02, . . . , R08 connected in series forming the resistor R0 to have equal resistance values, and changing the ratio of the resistance values of the resistors R0, R1, . . . , R7 each composed of 8 resistive elements so that the ratio effects the γ correction.
The liquid crystal panel 901 is alternatingly driven (driven by AC) to prevent liquid crystal polarization. There are two types of reversal drive schemes: “dot-reversal drive scheme” and “line-reversal drive scheme.”The following description will assume that the liquid crystal panel 901 has 6-row by 5-column pixels (picture elements) and driven by 6 gate signal lines and 5 source signal lines.
First, as related art, the liquid crystal display constructed as above will be described in terms of operation when it is driven by line-reversal drive scheme.
FIG. 19 is a timing chart showing scan signals S11a-S11f applied respectively to the 6 gate signal lines from the gate drivers 903 in the liquid crystal display as related art.
FIG. 20 is a timing chart showing, in the liquid crystal display as related art, any one scan signal S11 of the aforementioned scan signals S11a-S11f one data signal S12 of those applied to the 5 source signal lines from the source drivers 902, and an opposite electrode drive voltage S13 applied to the opposite electrode 907.
Now, FIGS. 19, 20 will be described collectively.
The scan signals S11a-S11f are HIGH only during a predetermined single horizontal synchronization period WH in each predetermined frame display period CH and LOW during the rest of the period. The scan signals S11a-S11f are HIGH at different times in each horizontal synchronization period. Therefore, the aforementioned voltages to be held in the pixels are written to the pixels in a row of pixels on one of the gate signal lines when the scan signal on that gate signal line is HIGH. A “row of pixels on a gate signal line” refers to a set of pixels having pixel electrodes connected to respective drain terminals of TFTs of which the gate terminals are in turn connected to the gate signal line.
The AC component of the opposite electrode drive voltage S13 applied to the opposite electrode 907 has a cycle equal to the horizontal period WH. In other words, in line-reversal drive scheme, normally, the opposite electrode 907 is AC driven at the same cycle as the horizontal period WH by a single constant voltage (5 V) power supply, and its electric potential (opposite electrode drive voltage S13) varies between the power source voltage level (5 V) and the GND voltage level (0 V).
Centered with respect to the amplitude center of the AC component of the opposite electrode drive voltage S13 applied to the opposite electrode 907, the AC component of the data signal S12 (the output of the source drivers 902) varies at a predetermined cycle less than, or equal to, the horizontal period WH. The amplitude of the AC component of the data signal S12 varies in accordance with the pixel tone. The AC component of the data signal S12a when the pixel tone is maximum, that is, the pixel is made to appear black, and the AC component of the data signal S12b when the pixel tone is minimum, that is, the pixel is made to appear white, have the same amplitude, but of opposite polarity.
The amplitudes of the data signals S12a and S12b when the pixel tone is maximum and minimum are both smaller than the amplitude of the AC component of the opposite electrode drive voltage S13 applied to the opposite electrode 907.
The arrows S14a, S14b indicate the polarity of the electric current flow through the pixel to write the aforementioned voltage to be held in the pixel, in other words, how much greater or smaller the voltage S12b to be held by the source signal line is than the voltage (opposite electrode drive voltage S13) held by the opposite electrode 907 when the aforementioned voltage to be held in the pixel is written to the pixel.
The arrows S14a, S14b, if pointing upwards, indicate that the voltage of the source signal line (data line) is higher than the center voltage (S13) of the opposite electrode 907; therefore the polarity of the electric current flow through the pixel is positive. If they are pointing downwards, it indicates that the voltage of the source signal line is lower than the center voltage (S13) of the opposite electrode 907; therefore, the polarity of the electric current flow through the pixel is negative. When the polarity of the electric current flow through the pixel is positive, the electric current flows from the source signal line, passes through the pixel, and travels on toward the opposite electrode 907. When the polarity of the electric current flow through the pixel is negative, the electric current flows from the opposite electrode 907, passes through the pixel, and travels on toward the source signal line.
“(a)” in FIG. 21 shows the polarities of the electric currents through all the pixels to write the aforementioned voltages to be held in the pixels to all the pixels in the liquid crystal panel 901 in a certain frame (suppose the first frame) when the liquid crystal display is driven by line-reversal drive scheme.
“(b)” in FIG. 21 shows the polarities of the electric current through all the pixels in a subsequent frame to the frame in (a) in FIG. 21 under the same conditions. The rectangles laid out in matrix represent the respective 6-row by 5-column pixels in the liquid crystal panel 901. A row of rectangles represents a row of pixels. A column of rectangles represents a column of pixels, that is, a set of all pixels having pixel electrodes connected to a source signal line via TFTs. When the polarity of the electric current flow through the pixel is positive, “+” (positive polarity) is written in the rectangle representing the pixel; when the polarity is negative, “−” (negative polarity) is written in that rectangle.
So far was a description of a drive device to produce a tone display using a TFT scheme liquid crystal display.
Incidentally, liquid crystal displays have been developed in response to demands for increased screen size to find ways to television and personal computer display market. Meanwhile, recent rapid market expansion of mobile telephones and game machines has created demands for more mobile-oriented liquid crystal displays and liquid crystal drive devices mounted thereto.
Basically, liquid crystal displays and liquid crystal drive devices must have compact screens to be suitable for such use in mobile terminals. Therefore, for that use, liquid crystal drive devices are also strongly required to be compact, lightweight, and low power consuming (for longer battery life), as well as to improve display quality and reduce cost.
However, the conventional standard voltage generating circuit 1019 have following problems. Optimal γ correction is performed (the zigzag line properties of the liquid crystal drive output voltage in FIG. 18) varies depending on the pixel count in the liquid crystal panel 901 and the type of liquid crystal material, hence from one liquid crystal display to another. Besides, the resistance division ratio of the standard voltage generating circuit 1019 built in the source driver 902 is determined in designing the source driver 902.
Therefore, if γ correction characteristics are to be changed in accordance with the type of chosen liquid crystal material in the liquid crystal panel 1 and the pixel count in the liquid crystal panel 1, the source driver 902 must be remade every time such a change occurs. This is a problem.
As a method of changing γ correction characteristics of related art, a method is conceivable which adjusts reference voltages (halftone voltages) supplied to the halftone voltage input terminals V′0-V′64 of the standard voltage generating circuit 902. However, the aforementioned adjusting method results in increased terminal counts and circuit size, and resultant added manufacturing cost. This is another problem.